1. Field of the Invention
The present invention relates to a power switch circuit, and particularly relates to a power switch circuit having a protection function of protecting an output transistor when an abnormal state occurs in the power switch circuit.
2. Description of Related Art
As the switch circuits which handle large electric power, many power switch circuits using power MOS transistors are used. Such a power switch circuit is sometimes loaded with the protective function of protecting the circuit by detecting the overheat state and overcurrent state of a semiconductor device. The protective function can be realized by, for example, a gate resistance which is provided between a gate terminal of a power MOS transistor and an input terminal which inputs therein a drive signal for the power MOS transistor, and a MOS switch for a protection circuit, which is provided between the gate terminal and the source terminal of the power MOS transistor. In the power switch circuit, when the power MOS transistor is in an overheat state, a current is passed to the gate resistance by turning on the MOS switch for the protection circuit, and a voltage between the gate and source of the power MOS transistor is decreased to turn off the power MOS transistor, whereby element breakdown due to overheating is prevented.
As the gate resistance for realizing the above described protective function, the resistor having a fixed resistance value is generally used. However, when the resistance value of the gate resistance is set to be small, there is the fear that a current continues to be passed to the gate of the power MOS transistor from the input terminal at the time of an overheat state to break the device. Meanwhile, when the resistance value of the gate resistance is set to be large, there arises the problem that the switching speed of the power MOS transistor becomes low due to voltage drop at the time of the normal state. An art of avoiding the problem when the resistance value of the gate resistance is fixed is disclosed in Patent Document 1.
FIG. 7 shows a block diagram of a semiconductor device (hereinafter, called a power switch circuit 100) described in Patent Document 1. As shown in FIG. 7, the power switch circuit 100 has a variable resistor 111, an abnormality detecting circuit 112, a power switch element (called a power MOS transistor) 113, and a gate cutoff MOS 114. Further, in the power switch circuit 100, a load is connected between an output terminal OUT and a power supply 102. The variable resistor 111 in Patent Document 1 is an element in which a MOS structure is formed by polysilicon and an N-type diffused resistor.
A drive circuit (not illustrated) is connected to an input terminal IN of the power switch circuit 100, and supplies a high signal to the input terminal IN of the power switch circuit 100 at the time of a normal operation. The high signal is supplied to a gate terminal of the power MOS transistor 113 through the N-type diffused resistor connected to aluminum wiring via a contact. The variable resistor 111 connects the input terminal IN and the gate of the power MOS transistor 113 via the N-type diffused resistor which is formed at a lower portion of the polysilicon, at the time of the normal operation. Meanwhile, at the time of an abnormal state, the N-type diffused resistor formed at the lower portion of the polysilicon is in a cutoff state, and therefore, the variable resistor 111 connects the input terminal IN and the gate of the power MOS transistor 113 via the N-type diffused resistor formed in a region around the polysilicon. More specifically, the variable resistor 111 connects the input terminal IN and the gate of the power MOS transistor 113 with a low resistance at the time of a normal operation, and connects the input terminal IN and the gate of the power MOS transistor 113 with a high resistance at the time of an abnormal state.
Patent Document 2 discloses the one in which the variable resistor 111 in Patent Document 1 is configured by using a P-channel MOSFET. Further, Patent Document 3 discloses the one in which the variable resistor 111 in Patent Document 1 is configured by using a J-FET. The output of the abnormally detection circuit shown in Patent Document 1 to 3 each is applied to the control gate of FET constituting the variable resistor.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2005-93763
[Patent Document 2] Japanese Patent Application Laid-Open No. 6-244414
[Patent Document 3] Japanese Patent Application Laid-Open No. 5-198801